Today, the company unveiled FPU3.0, its latest ASIC architecture aimed at enhancing AI inference and blockchain performance. The FPU series is Nano Labs’ proprietary ASIC chip architecture ...

This is a high-throughput computing chip based on the FPU architecture with a chip area of 800mm 2, which is the largest 3D packaged near-memory computing (NMC) chip. Computing in the era of big ...

The Nano FPU architecture comprises four fundamental modules and IPs: the Smart NOC (Network-on-Chip), the high-bandwidth memory controller, the chip-to-chip interconnect IOs, and the FPU core.

Today, the company unveiled FPU3.0, its latest ASIC architecture aimed at enhancing AI inference and blockchain performance. The FPU series is Nano Labs’ proprietary ASIC chip architecture tailored ...